• ARM A64 Page table
    Hi, I have a question on ARM page table. I am running a bare metal application on Cortex A72 and i have a failure with my application. Upon debugging the failure, i found an address which is contributing...
  • When are A32 state and A64 state determined?
    hi, expert i study ArmV8 architecture.   On taking an exception to a higher Exception level, the Execution state either:     • Remains unchanged.     • Changes from AArch32 state to AArch64 state.   i...
  • The A64 ISA and Compilers
    Fact: The ARM architecture is the most widely licensed 32-bit embedded instruction set architecture in the industry. That fact makes the ARM Instruction Set Architecture (ISA) incredibly important...
  • Coprocessor instruction differencies?
    Are there differences between coprocessor instructions and instruction2:s? I mean: MCRR vs. MCRR2 MRRC vs. MRRC2 MCR vs. MCR2 MRC vs. MRC2 LDC vs. LDC2 STC vs STC2 I didn't find any differences in the...
  • Does the ThunderX CP processor support AArch32?
    It's my understanding that AArch64 is supposed to be backward compatible with AArch32, at least that is what the documentation says. But, I found one (1) page at https://en.wikichip.org/wiki/cavium/thunderx...