• Code for integer division on Cortex-A8?
    Hi all, when I wrote a C code with division operation the compiler is generating some library calls.....when I tried to see the equivalent code for those function calls...I'm unable to reach there (may...
  • is it necessary for ARM-v8 soc to flush L2 cache to DRAM ?
    hi : I know , we can flush L1 I/D cache items to PoU with kernel interface(flush_cache_*). however, I can not find any clue about flushing L2 cache to DRAM(if without L3).  and I saw some points that...
  • Is PORESETn necessary to make a debugger work correctly?
    According to the Cortex-M3 trm r2p0(Issue H), Cortex-M3 has 3 reset input signals, PORESETn, SYSRESETn, and DAPRESETn. Now I am thinking about a SOC with SW-DP and thinking of reducing the number of...
  • how to know the specific cycles of every arm instruction (armV7,cortex-a8) while executing in asm file?
    how to know the specific cycles of every arm instruction (armV7,cortex-a8) while executing in asm form? if there are some documents which describes it in detail? In Chinese: 我目前用cortex-A8(armV7)来开发项目...
  • A8: Keeping Cache-enabled and MMU-disabled
    Hi all, A Question about the A8 processor. If I enable the L1 and L2 caches, I see a performance boost even if the MMU is disabled. I was under the impression that the MMU is required to be enabled...