• How many cycles requires the instruction QBNE?
    QBNE (Quick branch not equal) Using the PRU in the Beaglebone black (AM335x 1GHz ARM® Cortex-A8) I am asking how many cycles requires the instruction QBNE? qbeq myLabel, r1, 0 I suppose two if the comparison...
  • Question about a code snippet on ARM, Thumb state change
    Hi, I find the following code snippet online on ARM state change. Although that whole material looks solid, the second line in the blue code below is puzzling. add R1,PC,#1 ;Load address of SUB_BRANCH...
  • How many clock cycles do SVC/PUSH/POP/SRS/RFE insturctions take to execute on Cortex-A8 processor?
    I'm trying to count the cycle timing of my program in hand. I read the ARM Cortex-A8 R3P1 Technical Reference Manual: Chapter 16. Instruction Cycle Timing, but I couldn't find the cycle timings of SVC...
  • [Cortex-M0] Thumb mode & code size
    Hi, I'm somewhat confused with the Thumb mode code size.  My understanding is compiling with ARM mode will generate 32-bit instructions and compiling with Thumb mode will generate 16-bit instructions...