• How to set up stage-2 translation table
    Hi, I am trying to enable stage-2 translation for Armv8 aarch32, cortex-a53. If I set HCR.VM=1(enable stage-2 translation) it will crash. I suspect it does not set up stage-2 translation table. But...
  • Why there is no translation tables concatenation for stage 1 of VA translation?
    It is possible to concatenate tables in stage 2 and therefore gain performance by skipping a translation level. Since the HW must be set for it why not to enable concatenation in stage 1 as well and potentially...
  • Arm64 Long Format Translation Table Walk
    Hi all - I'm trying to understand stage 1 translation. Assuming that the translation is starting at level 2, how do you determine the number of page table entries in the level 2 table? The documnetation...
  • Explain 8 stage pipeline of ARM Cortex a7?
    Brief explanation of each stage of ARM pipe-lining. How many Neon pipeline stages are their? What is dual issue in ARM pipe-lining?
  • translational table : block and table descriptor
    Hello Experts, I am trying to understand in the attached snapshot, how the values of m and n are derived for table and block descriptors respectively ? Can anyone please explain me since I am...