• ARMv7-A: Cache maintenance operation by VA, performance
    Hi, according to this talk , cache maintenance should always be performed by VA and not by set/way except during boot or shutdown. However, invalidating/cleaning a block of data by VA requires a loop...
  • L2 cache with cortex-A8
    Hello, Can I assume that with cortex A8 cache invalidate/flush is used only with L1 ? I have some 2 implementation of this routines, one is called L1 and the other L2C-310. I am just not sure if using...
  • Cortex-A8 Pipelined cache maintenance
    Hi, I am new to the Cortex-A8, I would like to know what is the advantages of using "pipelined cache maintenance operations". "Auxiliary Control Register " has the "Cache maintenance pipeline" bit enabled...
  • Cache type and cache operation sequence
    I have a shared memory in DDR  --- shared between two separate ARM execution environments (say A and B)  in a heterogeneous compute SoC. SW on each execution units (A and B) Reads and Writes to this shared...
  • The merit of data cache cleaning
    Hello everyone, my 1st question to the ARM community; please excuse my ignorance.  Fairly recently, I shared OCM (on-chip-memory) on Xilinx Zynq processor (which is dual ARM Cortex A9).  To pass message...