• ARM cortext A53 Physical Address Flush
    Since ARM caches are physically indexed is there any way to flush based on the PA? I know I can get the set, but what about the way? If I am flushing from L1 would I have to flush all ways in L1 and then...
  • Barrier after access to memory mapped register?
    Hi, Iam wondering if it makes sense to have a memory barrier after access to a memory mapped register. I looking at a driver, unfortunately not open source, that has a memory barrier after a read from...
  • A53 preload mechanism
    Hi, I am reading the A53 MP Core doc. My question is related to instruction preloading in aarch64. In case of a very large block of code with no function calls, I want to make sure the L1 cache...
  • Cortexa53 AARCH64 context switch
    I have been trying to do a preemptive context switch on interrupt on the Cortexa53 but it isn't working can anyone spot an error in the code. The code has no FPU use so it is supposed to be just a lazy...
  • System level Implementation of Generic Timer in Cortex A53
    Hi, Im new to ARM. Im learning generic timers in cortex a-53. I wanted to know whats the meaning of "system level implementation" of Generic Timer and "PE implementations" of the Generic Timer. How...