• shareable attribute in armv8
    Hi Experts,                     I was going through the arm v8 mmu page table formation, when it's compared to arm v7 it is completely different. I could see how to set the different page attributes like...
  • shareability attribute for armv8 cortex a-53
    Hi, I have a system with a multiple quad core clusters with Cortex A-53 and the CCN-512. L1 through L2 are integrated caches where L3 is an outer cache in 8xHN-F of the CCN512. My question is how...
  • Using shareable attribute in MPU configuration of Cortex R4
    Good day all, I'm working with a SOC with dual Cortex-R4 that comes with MPU. Due to the SRAM limitation and other restrictions, I'm not using any embedded linux or any other SMP RTOS. Currently I'm working...
  • Why linux set memory as inner shareable in multi-cluster ARMv8 cores?
    Hi, I have board with two clusters, one has 4*A57 cores, and the other has 4*A53 cores. The A57 cluster has its own L1 and L2 cache, A53 cluster also has its own L1 and L2 cache. Between the clusters...
  • shareable domain and cache policy problem
    Hi, I'm trying to find out what level is the out-most level of inner shareable domain. Is there any register to get this information? I want to know what inner shareable domain is in A53 big-LITTLE...