• MRS/MSR (Banked register)
    What can be accessed by MRS/MSR in user mode? In ARMv7-A/R ARM there is an encoding for ARMv7VE (A1): B9.3.10      MSR (Banked register) cond  0 0 0 1 0 R 0 0        M1      Rd  (0) (0) 1 M 0 0 0 0 (0...
  • Register 'names' in instruction descriptions
    The registers in the instructions are usually 'named' Rn, Rm, Rd, ... Is there some deeper meaning in the names? Usually Rd seems to mean 'destination register' Sometimes Rn is the only operand, sometimes...
  • I cannot write the sp register in the monitor mode
    I use a Cortex-A7 board and write start up code. I try to use Security Extension. I use `smc` instruction and make cpu mode monitor mode. In the monitor handler, I tried to changed stack pointer value...
  • Cortex-A8 - accessing banked registers from monitor mode
    Note: This was originally posted on 20th March 2012 at http://forums.arm.com Hi Group, I am working on a Cortex A-8 Processor (ARMv7-a architecture). I am in the monitor mode and trying to access SP of...
  • Trustzone FIQ latency measurement When security extension is enabled
    Hello Guys, Please refer below attached image. as shown in this image i want to measure the different latencies in my Trustzone based application. Here is the list of measurements which i want to...