• Pipeline and Reorder Buffer on Cortex A9
    Hi everyone, For research reasons, I'm looking for information about the Cortex A9 out-of-order pipeline and the renaming of registries and any other data structures, if any, such as the reorder buffer...
  • Usage of gathering and reordering in the ARMv8
    Hi all, Kindly suggest some logical code to realize the gathering and re-ordering attribute in the ARMv8. How this attribute can be best utilized for actual use case scenarios ?
  • Efficient uasage of PLD instruction in combination with Load instructions?
    Hi all,  after a long time I'm back to forum with a question I'm posting this question with some pseudo code for(i=0;i<100;i++) { instruction1 instruction2 instruction3 ................. instructionA...
  • ARMv7-A: Cache maintenance operation by VA, performance
    Hi, according to this talk , cache maintenance should always be performed by VA and not by set/way except during boot or shutdown. However, invalidating/cleaning a block of data by VA requires a loop...
  • L2 cache with cortex-A8
    Hello, Can I assume that with cortex A8 cache invalidate/flush is used only with L1 ? I have some 2 implementation of this routines, one is called L1 and the other L2C-310. I am just not sure if using...