• GIC-v3: control of group 0 interrupts activation and selection
    Hi, I have two main questions, about the handling of group 0 interrupts: from my understanding of the GIC-v3 documentation, any secure OS (EL1, SCR.NS == 0) has access to ICC_IGRPEN0_EL1: Am I correct...
  • Get current active interrupt priority
    Hi everybody, We are working on a simple priority RTC (run to completion) framework for the Cortex M3/M4. Thanks to the NVIC/BASEPRI, we got most of this functionality for free but we want to extend it...
  • How to acknowledge/clear active interrupt in Cortex-M4
    Hi all, I'm testing interrupt on a Cortex-M4 based platform. So far I have managed to get my interrupt handler called. It clears the interrupt source coming from the peripheral. But before the pin to...
  • Understanding of the clock cycle activity for LPC1114
    Hello, I am now working with the LPC1114 which utilizes the ARM CORTEX M0 architecture. I have one question about the instruction set summary of the ARMv6M Thumb instruction set. I want to know what...
  • Pros and cons of activating cache in stm32F7
    Hi dear friends, I want to investigate whether it is better to activate caches in stm32F7 or not. For this purpose, I have studied stm32f7 reference manual and I have some questions about what I have...