• Cortex-M0+ privileged/unprivileged extensions
    Hi all, According with ARMv6-M architecture reference manual, it supports two operation modes, handler mode and thread mode. - "execution in handler mode is always privileged." - "execution in...
  • Cortex-A8 boot up cpsr status
    Hi, I have a beaglebone black and running a very basic app using starterware. As soon as the app starts executing i copy the CPSR values in memory. The value of CPSR is super surprising 6000019f which...
  • "CPSIE I"on an ARMv7A not changing the I bit in the CPSR register in USR mode - why?
    I'm using a CortexA8 and I can't seem to enable interrupts...! I'm using a "CPSIE I" instruction, I can see that the compiler (GCC) is not optimizing my code out... I have to manually stop the program...
  • CPSR status back to C variable
    Note: This was originally posted on 17th November 2008 at http://forums.arm.com Im using the TI Code Composer suite with an ARM 7 and Im looking for a way to get the CPSR back into a C variable. I was...
  • wfi in debug mode
    Hi, Please help me understand expected behavior of CM4 when CM4 is in debug mode and WFI is executed through single step. Does CM4 enter sleep/sleepdeep in such case ? Thanks, Sandeep