• Support for pipelining flops in AXI
    Hi All, Does ARM support pipelining flops in between valid/ready signals?Can someone explain why its *not* possible? Thanks
  • Cortex-A53 backward compatible with AXI-4 interconnect
    Hi, The Cortex-A53 core supports either ACE or CHI as its master interface. Assuming I don't need any of the coherent features introduced in the ACE specification, is there any functional problem if...
  • Cortex-A9-PL310 AXI connection
    Hi experts, I would like to know more about the interconnection between Cortex-A9 and the PL310 L2 cache controller. I think Figure 1.2 in the TRM is a good starting point: CoreLink Level 2 Cache Controller...
  • ARM v8 A64 instruction 32-bit variant usage
    Dear sirs, I'm studying ARM v8a architecture recently. I found that almost each A64 data processing instruction has a 32-bit variant using sf to encode it. My question is as follows. 1. who is responsible...
  • arm cortex a9 c++ support
    Hello, I'm new to arm cortex a9. how good does the compiler support C++11 or C++14 on bare metal? where can i find the latest compiler? I use Xilinx Zynq 7010 SoC, which comes with a Dual ARM® Cortex...