• Guidelines on reducing Cache Miss rate
    Hi Experts, Is there any document on general software guidelines in reducing the cache miss rate in the system for ARMV7 architectures ? If it is more specific to A/R/M then its great..
  • cache invalidation
    Hi, If the Cache line valid bit in implemented in the Memory along with the Tag RAM, during the initial power-up and reset, cache-invalidation requires each bit of the cache line to be explicitly written...
  • Cache ECC in Cortex-R5 & Event bus
    Hi everybody, I am using a Cortex-R5 embedded in a TMS570LC4357, and I am wondering to use the cache configuration as "Do not generate Aborts, force write through, enable hardware recovery". As far...
  • When the data CPU wants to access is not in the cache the related block will always be copy to the cache, is this right?
    When the data CPU wants to access is not in the cache the related block will always be copy to the cache, is this right? In the above question, the related region refers to the region seted to be cachealbe...
  • Cortex-A53 Cache protection
    Hello all, The "Core Technical Reference Manual" specifies in chapter 8.2 the error reporting mechanism for all types of uncorrectable errors in the caches, except for L1 D-cache data (which is SEC...