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  • Non aligned access in arm v7 going into exception
    typedef struct __attribute__((__packed__)) { uint8_t    op_code; uint8_t    flags; uint32_t   logical_block_addr; uint8_t    group_num; uint16_t   tx_length; uint8_t    control; } SCSI_READ10_t; when...
  • ARM Processor board and Programming
    I am trying to develop an ARM development board using ATSAM3U4C with a 96 MHz clock, a few LEDs and a button for external interrupt. Shown below is a little circuit that I have put in place. Using Atmel...
  • Why L1 cache associativity DOUBLED and index method CHANGED from the programmer's point of view?
    I'm confused when I see the description of L1 cache: L1 data memory system: The L1 data cache is organized as a Virtually Indexed, Physically Tagged (VIPT) cache. *Note* In the L1 data memory subsystems...
  • CAT Cache Allocation Technology) and CDP (code and Data Prioritization) features support
    Hi, XEN 4.7 (last version of Hypervisor Xen) is supporting following cache features:   - CAT Cache Allocation Technology   - CDP Code and Data Prioritization Those features are supported by x86 L3 caches...