• Cortexa53 AARCH64 context switch
    I have been trying to do a preemptive context switch on interrupt on the Cortexa53 but it isn't working can anyone spot an error in the code. The code has no FPU use so it is supposed to be just a lazy...
  • Problem in understanding behaviour of GCC compiler (aarch64-none-elf-gcc) on Neon intrinsics for ARM cortex a53
    Hi, I am using IDE Xilinx SDK 2019.1 for my application and running it on ARM cortex a53 processor with Neon and floating point engine support available. I am working on a bare metal application. ...
  • compiler optimization options for ARMv8 GCC compiler on ARM cortex a53 (bare metal application)
    I am using ARMv8 GCC compiler(aarch64-none-elf-gcc) for my bare metal application on ARM cortex a53. I am using neon intrinsics with plain C in my code so I would like to ensure to use all optimization...
  • Partial register dependency neon
    I'm having trouble finding any informations on partial neon register dependencies. Take for example the following code: ld2 {v0.16b, v1.16b}[0], [x0] ld2 {v0.16b, v1.16b}[1], [x1] ld2 {v0.16b, v1...