• Enable and disable MMU page table caching in L2
    Hello, I am using a dual core Cortex A9 CPU and I want to enable MMU caching in L2. By default all the DDR memory region is set as non-cacheable. But then I want only the DDR regions allocated...
  • A8: Keeping Cache-enabled and MMU-disabled
    Hi all, A Question about the A8 processor. If I enable the L1 and L2 caches, I see a performance boost even if the MMU is disabled. I was under the impression that the MMU is required to be enabled...
  • Disabling the MMU
    Hello everybody! I am working on a IMX-6 and i have a little problem with the MMU. I want to write on some registers which are blocked by the MMU, so i want to disable it. I went on this page ARM Information...
  • Enable MMU and d-cache on ARMv8 for u-boot
    Hi, This question is for MMU and d-cache. When I tried to enable MMU and d-cache for u-boot I ran into Synchronous Abort handler while writing to PCIe device registers which I mapped as uncached memory...
  • ARM Cortex A9 - Enabling/Disabling the Caches
    Hello, I'm developing a custom bootloader for NXP i.MX6 DualLite (ARM Cortex A9). In this bootloader, I need to initialize ~50 MB of RAM to Zeros, this part executes really fast after enabling Caches...