• In Arm v7 mmu, stage2 translation cannot use short descriptors. WHY?
    ARM V7 document states: "In ARMv7-A short descriptors only be used at EL0 and EL1 stage 1 translations. They cannot, therefore, be used by hypervisors or Secure monitor code." Why stage2/hypervisors...
  • Why does ARM have 64KB Large Pages?
    The ARM720T user manual mentions small and large pages. Since the ARM 720T requires a 64KB page table entry to be duplicated 16 times in the page table, why not place 16 small page (4KB) entries to mimic...
  • Does load/store-exclusive violate Hypervisor Transparency?
    Hello Community, I am currently learning hypervisor design using ARM's virtualization extensions (on both ARMv7 and ARMv8). A note in the ARMv8-A reference manual (section D1.5) mentions: "In some systems...
  • Why ARM does not support 64bit for faulting address of IPA?
    I'm trying to understand how ARM architecture(ARMv8) support for faulting address in the virtualization environment. For the hypervisor, every device access from the guest must be trapped to emulate...
  • Arm64 Long Format Translation Table Walk
    Hi all - I'm trying to understand stage 1 translation. Assuming that the translation is starting at level 2, how do you determine the number of page table entries in the level 2 table? The documnetation...