• A55 cache lock
    hi, could you tell me whether cortex-A55 support cache lock function? which cache support it, L1 or L2 or L3 or all of them? THANKS
  • Push/Pop in Cortex A55 64bit mode
    Hi, Is there any alternate instruction for push/pop since it is not supported in the cortex a55 (64 bit mode)? Currently I'm doing the stacking of the processor register manually using STP/LDP instructions...
  • How can I get the number of non-cacheable access in CA-55?
    The PMU of CA-55 can not count non-cacheable access event. L1I_CACHE_ACCESS and L1D_CACHE_ACCESS does not count non-cacheable access. I want to distinguish cacheable access and non-cacheable access...
  • Arm Cortex-A55: Efficient performance from edge to cloud
    Have you heard? There are a couple of new CPUs in town... and they pack a punch! Of course, I am talking about the Arm Cortex-A75 and Cortex-A55 , the first Cortex-A processors based on the recently announced...
  • Updating PC register in aarch64 mode
    Is there a way to update the PC register in the aarch64 mode? When we are at aarch32, we can access PC register directly. But in aarch64 mode, there is no handle to PC register.