• How to design simple memory protection using MMU attributes & modes ?
    Hello, Can anyone give some points as to how to design simple memory protection model, of standalone OS application composed tasks, each has its own region/section with attributes such as read only...
  • shareability memory attribute
    Hi ARM experts,     For shareability attribute, have some confusions:     1 For a memory location with cacheability attribute, does hardware do "flush" action after "writing" to push data to end if shareability...
  • MPU config and memory attributes
    I want config STM32F746 MPU , In the ARM Cortex M7 generic user guide External RAM memory region (0x60000000 - 0x7FFFFFFF)(512MByte) has WBWA (write back write allocate) cache policy see this link ...
  • Regarding mismatched memory attributes and cacheability
    As described in ARM ARM (ARMv7), mismatched memory attributes for mapping a physical region would happen when either/all of the memory type, shareability or cacheability of aliases differ My question...
  • How SMMU will override the memory attribute of the master which have MMU/MPU embedded?
    For example, one M4 is a client of SMMU, and its MPU had been configured to map some memory(MEM_A) as inner outter write-back, how the configureation of SMMU context transcation table will affect the...