• About AHB5 protection control signals
    In AHB5, we have extended memory bits as [6:4] hprot. Previously we have [3:0] hprot. For implementation purpose, i treated [6:4] as a separate signal. This separate signal am qualifying based on some...
  • Cortex-A53 Cache protection
    Hello all, The "Core Technical Reference Manual" specifies in chapter 8.2 the error reporting mechanism for all types of uncorrectable errors in the caches, except for L1 D-cache data (which is SEC...
  • CM4: Is DAP immune to MPU protections?
    Can the DAP cause exceptions by performing illegal instruction in spaces protected by MPU or is it immune? Trying my hand at setting up MPU but I cannot get it to fire - thought it might not be possible...
  • TM4C129 - Protect the code from copy
    I am trying to evaluate ways to protect my embedded code from being read and copy from outside world. I wonder what are the popular ways used out there. Pls note that you still need the option to upgrade...
  • Memory protection unit - Cortex-M4
    Hi. I am writing back regarding MPU usage. I implemented it into the software in next ways (note, that program is quite simple - only privileged mode, no RTOS): 1. I enabled background region, thus all...