• MMU initialization for an ARM multicore system
    I am working on an Arria10 SoC which has dual ARM Cortex-A9 MPCore. And I work on bare-metal environment with Intel SoCFPGA’s hardware library(HwLib). On the shared SDRAM, I am planning to have dedicated...
  • Multicore SMP using Linux kernel
    Hi, I am just trying to learn the linux kernel booting process for arm32 Cortex A9 multi core SOC. I had understood the concept of booting in linux, but I am confused about the section where secondary...
  • ARMv7-A: Cache maintenance operation by VA, performance
    Hi, according to this talk , cache maintenance should always be performed by VA and not by set/way except during boot or shutdown. However, invalidating/cleaning a block of data by VA requires a loop...
  • Cache and store buffer maintenance in cortex-a8!
    Dear All, Technical data sheets for the ARM7500FE  and ARM7100 say that: "In the ARM Processor the cache will be searched regardless of the state of the C bit, only reads that miss the cache will be affected...
  • General Feature of Cortex processors on cache coherency
    Hi Experts, Is there any general feature available in the cortex processors to realize the cache lines by DMA through AXI ? I found some features like CCI module available to provide this feature in multi...