• Operation of ARMv7 pipeline for simple instructions
    I am new to ARM architecture and trying to understand ARMv7 pipelining.I am comfortable with armv7 instruction set Can anyon provied me simple example for operation ARMv7 pipeline with simple instrction...
  • Cache maintanance operation to PoC
    Hi experts, I'm quite confused about cache maintanance operation to PoC on Cortex-A9 (with PL310 L2 cache controller). I'm refererring to the following operations: - DCIMVAC, invalidate data cache by...
  • how to know the specific cycles of every arm instruction (armV7,cortex-a8) while executing in asm file?
    how to know the specific cycles of every arm instruction (armV7,cortex-a8) while executing in asm form? if there are some documents which describes it in detail? In Chinese: 我目前用cortex-A8(armV7)来开发项目...
  • What happens if an interrupt occurs as it is already disabled
    for ARMv7 architecture:What happens if an interrupt occurs as it is already disabled
  • page table Cachability bit effect!
    Hi experts, I really get confused with the page table cachability bit (c bit) effect (Cortex-A8) and need your help to find answer of my question. The questions is whether page table C-bit only controls...