• How to set secondary core's registers from primary arm?
    Hi all, Im working on Keystone II Tci6638k2k(4arm+8dsp) custom design board with u-boot. I understand that how u-boot working. U-boot gives entry point to other cores. Other cores take program counters...
  • As arm cortex R4 is a dual core processor, is there a concept of booting core (primary core) and secondary core?
    Cortex R4 processor architecture mentions the processor as dual core. Is there a concept of booting core(primary core) and secondary core? Please provide details on this aspect.
  • Unusual time in booting secondary cores on ARMV8 platform (Zynq MPSoc)
    Hi all, I am working on UltraZed-EG Starter Kit and trying to boot secondary A53 core from primary A53 core with an SMC call with 0xc4000003 as the identifier. I have measured the time taken to reach...
  • ARM cortex A53 PMU read from another core
    Hello. I would like to ask if it is possible to read the PMU of core0 from core1. So far i have work with an one core CPU and i use the MRS, MSR instructions to set the PMU. How to enable the PMUs...
  • Multi core L1 cache coherent
    Dear experts, I'm going to implement multi-core(4 cortex-a53) in my private OS. I have an issue which needs your confirmation. Q. When core0 invalidates the L1-cache and L2-cache at VADDR(Cached)...