• Disabling L2 cache for CPU1 (Zynq-7000)
    Hello people, we are trying to make AMP application on Zynq 7000 custom board. We have a FreeRTOS v8.2.3 and lwIP v1.4.1 running on CPU0, while baremetal application is running on CPU1 and this one...
  • Locked L2 cache (Pl310) Write issue through JTAG- Zynq 7000
    We are using a Zynq-7000 SoC, and we are trying to do read and write to a locked L2 Cache through JTAG. From JTAG, Read works properly but writes makes the specific cache line corrupted, Step 1 : Initial...
  • Pipeline and Reorder Buffer on Cortex A9
    Hi everyone, For research reasons, I'm looking for information about the Cortex A9 out-of-order pipeline and the renaming of registries and any other data structures, if any, such as the reorder buffer...
  • How to disable the branch prediction on armv8
    Hello, I am working with ARMV8 Cortex A72 architecture, i want to know can i turn off branch prediction? and how can i do it? best regards,
  • ACTLR[1] question in Cortex-A serias SOC
    hi, experts: I found ACTLR register definition is different between Cortex-A7 and Cortex-A9. I have some questions about out cache concept in Cortex-A7. 1. Some program disable outer cache by setting...