• GICv3 and aarch32
    Hi, I just started to port our secure OS on an armv8 board, with a GIC-v3. The EL1 non secure OS will be the vendor Linux OS, which runs in aarch64. The EL1 secure OS will be our secure OS, which runs...
  • Use GICv3 legacy support
    I'm using a cortex-a53 FVP model. It comes only with GICv3, but by reading the ICC_SRE_EL3.SRE bit I see this implementation has legacy support. Before leaving EL3 I configure all interrupts to group...
  • AArch64/GICv3:ICC_SGI1R_EL1: AFF1
    I wonder, is AFF1 in ICC_SGI1R_EL1 also a bit-mask or does it address directly the cluster? So does AFF1 == 3 address cluster 3 or cluster 0 and cluster 1.
  • GICv3: setting G1SEN / G1NSEN in GICD_CTLR
    During my experiment with GICv3 using ARM Foundation platform, I tried to set GICD_CTLR value from 0x0 to 0x37 (ARE S/NS + Enable G0, G1S and G1NS) and I got the surprise to see that the finale value...
  • Using the Stack in AArch32 and AArch64
    When reading assembly-level code for any of the AArch32 or AArch64 instruction sets, you may have noticed that the stack pointer has various alignment and usage restrictions. These restrictions are part...