• What will I get if I try to access SCR in cp15 when my core is in non secure mode.
    I know that when the core is in non secure mode (non TZ), the normal world software is not able to access SCR in cp15. But I'm wondering what consequence it will cause if such operations occur. Unexpected...
  • MMU table management during CPU mode switch
    Hello, I have been working on developing comprehensive Data Abort and Prefetch Abort handlers for our ARM Cortex A9 dual-core CPU. Among the exceptions which are covered by these handlers, I am now...
  • is it possible to flush/invalidate cache from user space for AARCH32
    Hi, When AARCH64 works at AARCH32 mode, is it possible to flush/invalidate cache from user space? i know AARCH64 can do that, but is it capable for AARCH32? i am working on a user space driver and i need...
  • Security State transitions - Processor Mode
    Edit: CONTROL.nPRIV is actually banked so I modified my question Hi, I have a question regarding S/NS state transitions and PE modes. From what I read in the ARMv8-M ARM there is no restriction...
  • What is meaning of Logical MMU ?
    Hi I have read in one of the ARM document for TrustZone that Within a TrustZone processor the hardware provides two virtual MMUs, one for each virtual processor. This enables each world to have a...