• About the snoop filter in CCI 550
    I see such a description about the snoop filter in CCI 550 TRM: " Arm recommends that you configure the snoop filter directory to be 0.75-1 times the total size of exclusive caches of processors that...
  • CoreLink CCI-500: exceedingly good (Infographic)
    It’s been a busy start to the year for ARM as the year kicked off with CES 2015 showcasing some of the amazing experiences the consumer electronics of today (and tomorrow!) can provide. We saw a lot of...
  • Does CCI-400 guarantees cache coherency between secure and non-secure worlds?
    Hi Experts, I'm developing some kind of Secure OS on A57/53 big.LITTLE SoC. While multi-core testing, I'm facing some wired problem on my world shared memory mechanism. When I run world shared memory...
  • Extended System Coherency - Part 3 – Increasing Performance and Introducing CoreLink CCI-500
    Chinese Version 中文版: 扩展系统一致性 - 第 3 部分 - 性能提升和 CoreLink CCI-500 简介 This week we announced the launch of a new suite of IP designed to enhance the premium mobile experience. A central part of this suite...
  • AXI SLAVE PERIPHERAL
    Hi everyone! Please help me.. i have a project with a custom axi slave design that implements multiple memory ranges 256 words each . A master ( my processor in figure) can write burst data to the example...