• how "Early Write Acknowledgement" is encoded on AXI AxCache ? equal to "bufferable"?
    ARMv8 introduces this new attribute of memory type. (B2.8.2) And also it recommends that "early write acknowledgement" attribute should be exported to interface between PE and interconnect fabric. ...
  • How to acknowledge/clear active interrupt in Cortex-M4
    Hi all, I'm testing interrupt on a Cortex-M4 based platform. So far I have managed to get my interrupt handler called. It clears the interrupt source coming from the peripheral. But before the pin to...
  • What is the "Integer divide unit with support for operand-dependent early termination"?
    We are evaluating the CM33. The CM33 documentation mentions " Integer divide unit with support for operand-dependent early termination", what does it mean by "operand-dependent early termination"? Thanks...
  • ITCM, DTCM and IRAM access
    Note: This was originally posted on 28th March 2012 at http://forums.arm.com Hi, The ITCM and DTCM are used to improve the performance or the access speed (Low latency memory and Unpredictibility of the...
  • what is the difference between the device memory and the strongly-order memory ?
    Note: This was originally posted on 21st June 2011 at http://forums.arm.com Dear All,        Both device and strongly-order memory are used to model memory-mapped peripherals and I/O locations in ARMv7...