• why inner attribute is affected by outer configuration?
    Hi expert: I am configuring a CortexA15 system. In the LPAE page table entry, SH[1:0] is configured as 11, so this is a Inner Shareable field. Then I need to set MAIR0.attr0 which is used by stage 1...
  • Inner/Outer share ability in Cortex R52
    I am trying to configure memory attribute for cortex R52 in our SOC which is having integrated L1 I/D Cache and no coherent agent.and having system RAM. system is having two clusters with two cores...
  • Inner/Outer Cacheability in Cortex V8-R
    I am trying to configure memory attribute for cortex R52 in our SOC which is having integrated L1 I/D Cache and no coherent agent.and having system RAM. system is having two clusters with two cores...
  • How to set inner of outer shareability on page table entry WITHOUT TEX remap??
    At first, sorry to my fool English. I want to know how to set to inner or outer shareable attribute on page table entry using TEX, C, B and  S bit (without TEX remap). I knew if i use TEX remap, the PRRR...
  • [ARMv7] question about writel & barrier
    Hi Sirs, I got a question about the way Linux 3.18 defines the "writel()". In linux-3.18/arch/arm64/include/asm/io.h, it describes: /* * I/O memory access primitives. Reads are ordered relative to any...