• Non-Cacheable memory and DMA on armv7a
    Hi ! Consider a micro-kernel (not Linux) where device drivers are userland applications (PL0). We would like to use DMA based device, like an Ethernet controller for example. To this mean, the micro...
  • Regarding mismatched memory attributes and cacheability
    As described in ARM ARM (ARMv7), mismatched memory attributes for mapping a physical region would happen when either/all of the memory type, shareability or cacheability of aliases differ My question...
  • Normal/Non-shareable/Non-cacheable memory note on Cortex-A5 TRM
    Does anyone know what means "Does not access L1 caches." note in the "Treatment of memory attributes" table from [1] for Normal/Non-shareable/Non-cacheable memory for Cortex-A5? Thank you! [1] infocenter...
  • What's the relationship between exclusive access and memory cacheable in Cortex A53?
    Hello community and experts, I am doing an experiment on Cortex-A53 which executes some exclusive access instructions such as 'ldaxr'. When I config memory to Normal type+cacheable, 'ldaxr' can execute...
  • Cortex-A9: Eviction of dirty line from the region marked as Only "Inner Cacheable" from L1 cache - will if be allocated into L2?
    Hello, Consider following scenario: A 4 KB page starting @0x80000000 is marked as Normal Memory, Inner Cacheable, write-back, non-shareable, non-outer cacheable, L2 is inclusive cache. Now, the s/w writes...