• EL1 behavior when MMU is off
    Hi, I am facing issues with EL1 Guest OS.  I have enabled EL2 stage 2 page tables and set up all the virtualization registers {HCR_EL2, VTCR_EL2 and VTTBR_EL2 etc.} I am mapping my Guest OS memory to...
  • AArch64/GICv3:ICC_SGI1R_EL1: AFF1
    I wonder, is AFF1 in ICC_SGI1R_EL1 also a bit-mask or does it address directly the cluster? So does AFF1 == 3 address cluster 3 or cluster 0 and cluster 1.
  • GICv3: setting G1SEN / G1NSEN in GICD_CTLR
    During my experiment with GICv3 using ARM Foundation platform, I tried to set GICD_CTLR value from 0x0 to 0x37 (ARE S/NS + Enable G0, G1S and G1NS) and I got the surprise to see that the finale value...
  • ARMv8 Secure EL1 problem
    Hi, arm experts, We want to use ARCH32 mode in secure EL1, I see some descriptions in ARMv8 Arch Reference Manual about Secure EL1 ARCH32 mode as follows: One is the VBAR(secure), it is mapped to  VBAR_EL3...
  • GICv3 and aarch32
    Hi, I just started to port our secure OS on an armv8 board, with a GIC-v3. The EL1 non secure OS will be the vendor Linux OS, which runs in aarch64. The EL1 secure OS will be our secure OS, which runs...