• Watchdog timer not entering ISR
    I am using ARM cortex A9 core in Zynq. I want to trap any bugs in hardware or my firmware. I intend to use watchdog module in interrupt mode and connect it to Global interrupt controller (ScuGic). When...
  • wrong reset value of TTBR0 at reset, in Cortex A9, R3P0
    Hi i have some questions on dual Core CortexA9 r3p0 revision. I am using Cortex A9 r3p0 processor in Our SOC(system on Chip). when i connect to Core 0 and read TTBR0 register i get 0x00004001, but when...
  • SP805 Watchdog Timer
    Hi, I am writing a driver for watchdog timer for my custom platform, what I am observing is, as counter 1st time reaches to zero , then it generates an interrupt and ISR is called if I clear this...
  • Issue about Cortex-A9 Dhrystone performance
    Hi, We found the following document on Cortex-A9 performance. List of ARM microarchitectures - Wikipedia, the free encyclopedia Which claims 2.5 DMIPS/MHz per core for Cortex-A9 2GHz@2 core. However,...
  • Locked L2 cache (Pl310) Write issue through JTAG- Zynq 7000
    We are using a Zynq-7000 SoC, and we are trying to do read and write to a locked L2 Cache through JTAG. From JTAG, Read works properly but writes makes the specific cache line corrupted, Step 1 : Initial...