• Count Main TLB miss
    Hello, experts: My platform is a Cortex-A9 MPCore CPU, Sabre Lite(i.mx6). I tried to count TLB miss so I implemented PMUEVENT to check micro TLB miss. But PMUEVENT doesn't support the main TLB miss...
  • Does ARMv8 SOC support cache lockdown?
    hi, experts: In ARMv8 Arch reference manual, it said: ARMv8 supports cache lockdown feature, but it is implementation defined. So, my question is: Has the integrated L2 Cache controller some registers...
  • AArch64 TLB maintenance requirements
    Hello all, I want to improve VM operation in AArch64 port of FreeBSD but I stuck on following problem. The FreeBSD VM subsystem is capable to map various *kernel* objects by using superpage (higher order...
  • Arm a53: Populate TLB without table walk?
    Hi, From a previous question I got that setting the EPDx bits from the TCR_ELx register to 1 will disable table walk. Good starting point. But, should I access the same memory location again, it won...
  • L2 TLB internal memory access through RAMINDEX
    Hi Experts, I need to access L2 TLB internal memory for A76 core (Section A6.6 of Cortex A76 TRM) . I was searching for an example code and found this for A57 core: LDR X0, =0x0000000001000D80...