• Exception / Interrupt for Cortex-A15
    Hi, I would like to know whether my understanding is right or not regarding to the interrupt (exception). When an interrupt is issued, the interrupt is executed at once without the completeion of the...
  • ARM cortex A15 hardware simulatenous multihreading.
    Dear All, Does ARM cortex A-15 support some kind of Hardware multithreading? how can I disable it? Thank you so much.
  • How to handle SCU at runtime on Cortex-A9
    Hi there, I'm working on altera cyclone V SoC equipped with a Dual Core Cortex-A9. It runs Linux socfpga 3.13. I'm trying to disable (and enable) the SCU at runtime, but I have a segmantation fault: unable...
  • Cortex-A15 MPCore: How to Enable Monitor Debug Mode
    Hi experts, I want to enable monitor debug mode for Cortex-A15 MPCore. I tried modifying DSCR[15] bit but watchpoint event still won't generate exception/abort. Core was in no-debug mode before modifying...
  • Cortex-A8/A15 L1 cache
    Hi, I would like to know whether the cortex-A8/A15 L1cache has ECC or parity check for error checking, or not. I know L2 cache has ECC function. Bur I don't know about L1 cache. Please let me know. Best...