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    hi, could you tell me whether cortex-A55 support cache lock function? which cache support it, L1 or L2 or L3 or all of them? THANKS
  • What can cause getting Cortex-A55 DSU P-Channel PACCEPT/PDENY signals fail?
    Hi experts, I do an experiment about cpu power with a board which has 4 cores of Cortex-A55. I try to power on/power off core1~3 parallelly. Sometimes Both PACCEPT and PDENY are zero after changes...
  • Arm Cortex-A55: Efficient performance from edge to cloud
    Have you heard? There are a couple of new CPUs in town... and they pack a punch! Of course, I am talking about the Arm Cortex-A75 and Cortex-A55 , the first Cortex-A processors based on the recently announced...
  • Using the Stack in AArch64: Implementing Push and Pop
    As described in my last article , AArch64 performs stack pointer alignment checks in hardware . In particular, whenever the stack pointer is used as the base register in an address operand, it must...
  • How many clock cycles do SVC/PUSH/POP/SRS/RFE insturctions take to execute on Cortex-A8 processor?
    I'm trying to count the cycle timing of my program in hand. I read the ARM Cortex-A8 R3P1 Technical Reference Manual: Chapter 16. Instruction Cycle Timing, but I couldn't find the cycle timings of SVC...