• Reordering between multiple loads
    Hello, I have a question if following sequence of instructions involving post-indexed LDRs could be re-ordered on say Cortex A8: To simplify, lets consider, r0 = 0xC, Cache line size 16 Bytes ldr    ...
  • Usage of gathering and reordering in the ARMv8
    Hi all, Kindly suggest some logical code to realize the gathering and re-ordering attribute in the ARMv8. How this attribute can be best utilized for actual use case scenarios ?
  • Cortex-A8 Pipelined cache maintenance
    Hi, I am new to the Cortex-A8, I would like to know what is the advantages of using "pipelined cache maintenance operations". "Auxiliary Control Register " has the "Cache maintenance pipeline" bit enabled...
  • Interrupt on Out-of-Order pipeline of Cortex-A15
    Hi, I would like to know the interrupt behavior on Out-of-Order pipeline on Cortex-A15. When some instruction is executing on Out-of-Order pipeline, one interrupt is happens. In this case, its interrupt...
  • Explain 8 stage pipeline of ARM Cortex a7?
    Brief explanation of each stage of ARM pipe-lining. How many Neon pipeline stages are their? What is dual issue in ARM pipe-lining?