• How to handle SCU at runtime on Cortex-A9
    Hi there, I'm working on altera cyclone V SoC equipped with a Dual Core Cortex-A9. It runs Linux socfpga 3.13. I'm trying to disable (and enable) the SCU at runtime, but I have a segmantation fault: unable...
  • Cortex A15 SCU
    Hi, I find no introduction about SCU registers of A15 in the TRM. So, can software control SCU? Especially is SCU needed to be enabled by software? Thanks&Regards.
  • TZASC (TZC380) enabling sequence
    Hi everyone, I am trying to correctly setup the TZASC of my IMX6q and IMX6ul boards, without blowing the fuse (I only have one board, I'd like to have it right by software before). From what I gathered...
  • ARM Cortex A9 - Enabling/Disabling the Caches
    Hello, I'm developing a custom bootloader for NXP i.MX6 DualLite (ARM Cortex A9). In this bootloader, I need to initialize ~50 MB of RAM to Zeros, this part executes really fast after enabling Caches...
  • M4 Assembly - Set Enable also enables the Clear Enable Interrupt Register
    Hi, I have some assembly for Cortex M4 (Arm 7M Thumb), I want to enable an interrupt that is connected to a push button on an STM32 F407. It works, but for some reason when I enable the set enable register...