• ARM cortext A53 Physical Address Flush
    Since ARM caches are physically indexed is there any way to flush based on the PA? I know I can get the set, but what about the way? If I am flushing from L1 would I have to flush all ways in L1 and then...
  • Could anybody tell me how to boot up a processor in AARCH32 bit mode in Arm V8 and A53 core?
    can you please tell me how to boot up a processor in 32 bit mode for Armv8, A53 core using baremetal code? how can i know it is booted in 32bit mode? Thanks.
  • A53 preload mechanism
    Hi, I am reading the A53 MP Core doc. My question is related to instruction preloading in aarch64. In case of a very large block of code with no function calls, I want to make sure the L1 cache...
  • Can we run the Cortex-A53 cores at different clock speeds ?
    Dear ARM Group, Can we run the A53 cores at different clock speeds? if YES,  How does it effect the complete A53 (L2 cache etc) and system? if NO,  What are the constraints ? could you please give a detailed...
  • help me to understand this assembly program for configuring MMU for ArmV8,A53.
    ******************************************************************************/ /*****************************************************************************/ /** * @file translation_table.s * ...