• Information about ARM System control registers.
    Hi all, I noticed there are multiple system control registers in ARM. The SCTLR_EL1 , SCTLR_EL2 and SCTLR_EL3. I want to know, what do multiple such system controls registers represent?? I am particularly...
  • Which register excactly control the endiness in the EL0 data access? SPSR_EL1 or SCTLR_EL1?
    Hello: Suppose all exception Ievels support both big and little endian operation. According to the ARMv8 ARMARM, when exception taken from AArch32 state, the SPSR_EL1.E bit can control the endianess...
  • Barrier after access to memory mapped register?
    Hi, Iam wondering if it makes sense to have a memory barrier after access to a memory mapped register. I looking at a driver, unfortunately not open source, that has a memory barrier after a read from...
  • ARM cortext A53 Physical Address Flush
    Since ARM caches are physically indexed is there any way to flush based on the PA? I know I can get the set, but what about the way? If I am flushing from L1 would I have to flush all ways in L1 and then...
  • Reset Management Register Functioanlity in ARM v8
    Hi Experts, Does the Reset Management Register will be implemented mandatory or optional for the SoC based on ARMv8 and how it is practically used ? Regards, Techguyz