• ARMv8 EL1 MMU
    Hi,     I am working on bootloader porting to ARM v8 platform. I am facing a problem in enabling MMU in execution level-1 EL1. I am not able to set sctlr_el1.M bit when ever i try to set this bit the...
  • could anybody help me to write a bare metal startup code for LS1043A (ARM V8,A53)in 32bit(AARCH32)mode
    excuse me for my English!!! i want to write bare-metal startup code in 32-bit mode for LS1043A-Rdb.it is having V8 A53 core. i have bare-metal 32bit(AARCH32) code for xilinx processor(which is of...
  • A53 - MMU vs MPU
    Do Arm offer A53 with only MPU? Because right now we have only one to one mapping. we just need to use MPU only. Yes I understand MMU is superset of MPU but can be expensive (performance wise). Or there...
  • Why the address width of MMU-500 is different with Cortex-A53/57?
    I find the description below from MMU-500 TRM. Address width The incoming address width is fixed at 49 bits, where A[48] specifies VA sub-ranges. You must tie all unused bits to zero. The output address...
  • ARMv8 mmu problem
    Hi ARM experts, I have a problem in using armv8 mmu in bare-metal system: When using the 4KB translation granule, level 1 table which use D_Block convert VA to 1GB region PA. In Armv8 ARM page D4-1744...