• why there are separate registers for interrupt set-enable and clear-enable while can be just one
    I can't understand why there are separate registers like Interrupt Set-Enable and Clear-Enable Registers or Interrupt Set-Pending and Clear-Pending Register in NVIC? these dual registers couldn't be handled...
  • CM4: Write buffer with enabled MPU
    Hello, I have a question regarding Memory protection unit on Cortex M4 (STM32F3 MCU). This is pretty simple single core MCU without caches. I implemented MPU based on instructions in Definitive guide...
  • Enabling NEON Instructions on Pixhawk
    I am trying to get a quadcopter flying using the Pixhawk controller (Cortex M4 running NuttX RTOS) and I am using the Simulink Pixhawk PSP to implement a custom controller. Our controller uses neural...
  • Cortex M7 irq enable/disable
    In the appnote "ARM Cortex-M Programming Guide to Memory Barrier Instructions" there is a section that describes the use of memory barriers in the Cortex-M processors on a case-by-case basis. Are those...
  • TZASC (TZC380) enabling sequence
    Hi everyone, I am trying to correctly setup the TZASC of my IMX6q and IMX6ul boards, without blowing the fuse (I only have one board, I'd like to have it right by software before). From what I gathered...