• NEON: Cortex A7 is 4 times slower than Cortex A8 ?
    I'm seeing Cortex-A7 cycle-timing table here : http://hardwarebug.org/2014/05/15/cortex-a7-instruction-cycle-timings/ For example,  VADD.F32 Dd, Dn, Dm takes 2 cycles VADD.F32 Qd, Qn, Qm takes 4 cycles...
  • Why Cortex-M7 doesn't support bit-banding?
    Cortex-M7 processors tends to be for the high performance applications. So why it doesn't support bit-banding if this has a lot of advantages to the code size and performance?
  • Why use Cortex-M7 dual-redundant core?
    Cortex-M7 has an parameter named "LOCKSTEP" which specifies whether the implementation is a dual-redundant core and uses lock-step. My question is: why do I need to implement the dual-redundant core...
  • Raising priority of PendSV within NVIC when PendSV pending
    Hi, I'm trying to understand the behavior of raising (lowering numerical priority) the priority of PendSV in the NVIC of a Cortex M4 or M7 when PendSV is already pending. Below are the cases I'm grappling...
  • Cortex-M7 "zero overhead loop"
    Hi. In the page 22 of the document below informs that the cortex-m7 has "zero overhead loops" capability. I would like to know how it is done? Is there a special instruction for it? http://community.arm...