• How to understand the behavior of hazard in Cortex-M4?
    Hello to all, I am working on Cortex-M4 and would like to know about the hazard situation. In order to see the effect of Data-Hazard, I have executed few application codes. For example, ...
  • what situation will the FPCA in Cortex-M4 change?
    Hi all, I'm study Cortex-M4 recently, and try to use floating point calculation, I read the book about that saying FPCA in control register will be set 1 after FPU work, but I'm not sure that when...
  • TCM arbitration hazard: Considerations for Firmware
    According to the ARM spec (ARM DDI 0460D section 8.4.4): TCM arbitration Each TCM port receives requests from the LSU, PFU, and AXI slave. In most cases, the LSU has the highest priority, followed...
  • Cortex M4 Conditional Branch - Pipeline
    Hello all! So I'm working on a development with a Cortex M4 and there is something i don't understand, I was hoping someone could help clarify this: This is the code I' using (Assume R3 content...
  • Question about the Pipeline, clock cycle and machine cycle in Cortex-M Series.
    Recently I'm learning the implement of ARM cortex m core in order to optimize my software to be more efficient and be easier to predict its execute time. But now I'm confused about the clock cycle, machine...