• CM4: Write buffer with enabled MPU
    Hello, I have a question regarding Memory protection unit on Cortex M4 (STM32F3 MCU). This is pretty simple single core MCU without caches. I implemented MPU based on instructions in Definitive guide...
  • ARM CM4 FPU execption
    I am looking for FPU exception generation code. If some one share, or suggest some document for the same. Regards Anuj
  • Question is on WIC-CM4 interface
    Hi, Assume system configuration is: CM4 in a switchable power domain and WIC in always on domain. Also in response to "seeldeep" if the power management unit is powering down the CM4 and with no logic...
  • CM4: Is DAP immune to MPU protections?
    Can the DAP cause exceptions by performing illegal instruction in spaces protected by MPU or is it immune? Trying my hand at setting up MPU but I cannot get it to fire - thought it might not be possible...
  • Where is the register definition of DHCSR for Cortex-M4
    The manual of Cortex-M4 defines the address of DHCSR but provides no information about the register format.