• Master to Master communication in AHB
    For example, I have an AHB bus with two masters: 1.ARM processor 2. Ethernet MAC , many slaves. The Ethernet MAC IP should be configured to generate the Ethernet Packets. Is there any way to use Processor...
  • PC doesn't update in simulation
    Dear All, Now I'm trying to digging the M3 operation in especially reset sequence with hello example of cortex design kit. Current situation is that reg14[31:0] is fixed in 0xFFFFFFFF and reg15[31...
  • First compile, verilog files missing
    Hi, I am just performing the first steps with the DesignStart Eval Edition (Cortex-M0), trying to compile the verilog sources to get a simulation running. So I changed /systems/fpga_testbench/trl_sim...
  • AMBA AHB SLAVE MULTIPLE SPLIT RESPONSES TO SINGLE MASTER
    Can the AMBA AHB Slave give multiple SPLIT response again to the AHB Master that has been given SPLIT response before and after updating hsplit signal for that Master by the Slave?
  • M0 verilog source code(GATEHCLK)
    Hi, - Our product need power management with cortex M0. - In the verilog cod we request from ARM, there is a output pin "GATEHCLK" In module CORTEXM0INTEGRATION, but it is floating. I think it is...