• Understanding interrupt latency and jitter in Cortex-M
    Hi, I've been trying to get a good grasp of the variables associated with interrupt handling in the Cortex-M family. I've read " A Beginner’s Guide on Interrupt Latency - and Interrupt Latency of the...
  • Cortex-M7 Load/store timing execution ?
    I'm not a native English speaker. So, sorry for the broken English. I'm intend to develop a system where the microcontroller will interface with a 8 bit parallel port IC. The bytes will be loaded into...
  • A Beginner’s Guide on Interrupt Latency - and Interrupt Latency of the Arm Cortex-M processors
    Introduction All experienced embedded system designers know that interrupt latency is one of the key characteristics of a microcontrolller, and are aware that this is crucial for many applications...
  • Exec latency for ASIMD instructions taking the V pipelines
    Hi, From the optimization guides for different Cortex A, for example Cortex A76, it seems that all ASIMD instructions (Integer or FP) taking the V pipeline (V0 or V1) have at least a latency of 2, even...
  • Cortex M7 cache ECC error
    Hi, I'm currently working on STM32H7 which run a cortex M7. I'm trying to figure out how an ECC error upon a look up in the instruction or data cache is reported to the core. The only mention I've...