• DMB, DSB, ISB on Cortex M3,M4,M7 Single Core parts
    I have been reading through the ARM documentation on memory and instruction barriers. I have read that the single core ARMv7-M parts do not reorder instructions, as such the DSB and ISB are not needed...
  • Cortex-M7 Load/store timing execution ?
    I'm not a native English speaker. So, sorry for the broken English. I'm intend to develop a system where the microcontroller will interface with a 8 bit parallel port IC. The bytes will be loaded into...
  • system requirements
    what are the minimum hardware requirements to setup wifi on arm-7 processors.
  • mismatch between ARMv7-M ref manual and core_cm7.h
    The ARMv7-M reference manual notes there eight ITM trace enable registers called ITM_TER0 to ITM_TER7. However, core_cm7.h only has one ITM_TER register. Can you clarify? Is it an error in core_cm7.h...
  • dsb and dmb
    Hi all: I have some questions about DMB and DSB in armv8. (1) In armv8 Reference Manual doc, it says " The DMB instruction does not ensure the completion of any of the memory accesses for which...