• Cortex-M MPU limitations
    Hi All, The title may seem a bit negative, just from my personal point of view. What is the main reason of the two requirements of setting up MPU, namely size and start addresses of MPU regions. First...
  • CM4: Write buffer with enabled MPU
    Hello, I have a question regarding Memory protection unit on Cortex M4 (STM32F3 MCU). This is pretty simple single core MCU without caches. I implemented MPU based on instructions in Definitive guide...
  • MPU
    Hi Using STM32f4 Board, I am enabling MPU in between any code (simple program) always causing memory management fault on debugging fault that ( IACCVIOL) bit is set, It means Attempting...
  • Cortex M7 irq enable/disable
    In the appnote "ARM Cortex-M Programming Guide to Memory Barrier Instructions" there is a section that describes the use of memory barriers in the Cortex-M processors on a case-by-case basis. Are those...
  • Cortex M7 cache ECC error
    Hi, I'm currently working on STM32H7 which run a cortex M7. I'm trying to figure out how an ECC error upon a look up in the instruction or data cache is reported to the core. The only mention I've...