• how to enable am335x Monitor debug-mode
    Hi , The monitor debug mode can be configured in DSCR, which is writable via APB interface for am335x. But,  I read the DRAR(MRC p14, 0, <Rd>, c1, c0, 0) and DSAR(MRC p14, 0, <Rd>, c2, c0, 0). Both of...
  • I cannot write the sp register in the monitor mode
    I use a Cortex-A7 board and write start up code. I try to use Security Extension. I use `smc` instruction and make cpu mode monitor mode. In the monitor handler, I tried to changed stack pointer value...
  • MRS/MSR (Banked register)
    What can be accessed by MRS/MSR in user mode? In ARMv7-A/R ARM there is an encoding for ARMv7VE (A1): B9.3.10      MSR (Banked register) cond  0 0 0 1 0 R 0 0        M1      Rd  (0) (0) 1 M 0 0 0 0 (0...
  • Funny asymmetry with banked register names
    Is there a reason why banked registers SP and LR can't be accessed as r13_<mode> or r14_<mode>, but one has to use SP_<mode> or LR_<mode> instead? It makes macros and inline assembly difficult. In document...
  • ARM Context ID Register & Process Context Switch
    Hi, all What is the content of Context ID Register of ARM Cortex A9. Is it OS that is responsible for assigning the value of Process ID and ASID? As far as I know, it is so in Linux. Is that the same...