• Where is hardware interrupt latency documented for the ARMv8 Cortex-A53?
    Need specific references to the hardware interrupt latency for the ARMv8 Cortex-A53.  interrupt latency from when an interrupt is triggered to when the ISR is initially invoked, but not including operating...
  • Synchronization of caches on ARMv8
    Hello, I have a question regarding the synchronization of caches on ARMv8 on Multi-Core. Let's assume that we have 2 cores that are running in parallel, and both has L1 Cache with line size = 64 Bytes...
  • ARMv8 PMU access
    Hey guys, I'm running a sw in a multicore ARMv8 system and I'd like to know a bit more about the PMU component. There is a PMU per CPU, right? Is it possible from one CPU to access the other CPU...
  • ARMv8 EL1 MMU
    Hi,     I am working on bootloader porting to ARM v8 platform. I am facing a problem in enabling MMU in execution level-1 EL1. I am not able to set sctlr_el1.M bit when ever i try to set this bit the...
  • ARMv8-A CurrentEL Register Definition
    Where is the register definition of the CurrentEL register ?. I cannot seem to find it in the ARMv8A programming model guide or the Cortex-A53 TRM. . How does the PSTATE bits map to CurrentEL ? I...